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PE4244
Product Specification
Evaluation Kit
The SPDT Switch Evaluation Kit board was
Figure 4. Evaluation Board Layout
Peregrine specification 101/0037
designed to ease customer evaluation of the
PE4244 SPDT switch. The RF common port is
connected through a 50 ? transmission line to the top
left SMA connector, J1. Port 1 and Port 2 are
connected through 50 ? transmission lines to the top
two SMA connectors on the right side of the board,
J3 and J4. A through transmission line connects
SMA connectors J6 and J8. This transmission line
can be used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom
layer provides ground for the RF transmission lines.
The transmission lines were designed using a
coplanar waveguide with ground plane model using
a trace width of 0.030”, trace gaps of 0.007”,
dielectric thickness of 0.028”, metal thickness of
0.0014” and ε r of 4.4.
J2 provides a means for controlling DC and digital
inputs to the device. Starting from the lower left pin,
the second pin to the right (J2-3) is connected to the
device CTRL input. The fourth pin to the right (J2-7)
is connected to the device V DD input. A decoupling
capacitor (100 pF) is provided on both CTRL and
V DD traces. It is the responsibility of the customer to
determine proper supply decoupling for their design
application. Removing these components from the
evaluation board has not been shown to degrade RF
performance.
Figure 5. Evaluation Board Schematic
Peregrine specification DOC-40137
Document No. DOC-30006-2 │ www.psemi.com
?2005-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 6
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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